------------------------------------------------------------------------------ -- PCI-to-PCI Bridge 21285 -- BSDL file ------------------------------------------------------------------------------ entity DS21285 is generic(PHYSICAL_PIN_MAP : string := "BGA_231_PACKAGE"); port (PAD_MAS : inout bit_vector(1 DOWNTO 0); PCI_IRQ_L : inout bit; SERR_L : inout bit; TX : out bit; XCS_L : inout bit_vector(2 DOWNTO 0); XIOW_L : inout bit; XIOR_L : inout bit; XD_WREN_L : inout bit; ROM_CE_L : out bit; D_WREN_L : out bit; PCI_GNT_L : out bit; CS_L : out bit_vector(3 DOWNTO 0); CMD : out bit_vector(2 DOWNTO 0); BA : inout bit_vector(1 DOWNTO 0); MA : inout bit_vector(12 DOWNTO 0); PAD_PARITY : inout bit_vector(3 DOWNTO 0); PAD_DQM : out bit_vector(3 DOWNTO 0); PAD_NRESET : inout bit; PAD_NFIQ : out bit; PAD_NIRQ : out bit; PAD_DBE : out bit; PAD_ABE : out bit; PAD_D : inout bit_vector(31 DOWNTO 0); PAD_A : inout bit_vector(31 DOWNTO 0); PCI_RST_L : inout bit; REQ_L : inout bit; PERR_L : inout bit; DEVSEL_L : inout bit; STOP_L : inout bit; TRDY_L : inout bit; IRDY_L : inout bit; FRAME_L : inout bit; PAR : inout bit; CBE_L : inout bit_vector(3 DOWNTO 0); AD : inout bit_vector(31 DOWNTO 0); NC : linkage bit; PAD_FCLK_OUT : linkage bit; PAD_MCLK : linkage bit; PAD_SDCLK : linkage bit_vector(3 DOWNTO 0); IRQ_IN_L : in bit_vector(3 DOWNTO 0); IDSEL : in bit; GNT_L : in bit; PCI_CLK : LINKAGE bit; -- Was: IN bit. Captures inverted data. PCI_CFN : in bit; VIO : LINKAGE bit; -- WAS: IN bit. 5v -> "1", 3.3v -> "0" ! PAD_OSC : in bit; PAD_FCLK_IN : LINKAGE bit; -- Was: IN bit. Captures inverted data. PAD_NRW : in bit; PAD_NMREQ : in bit; PAD_CLF : in bit; PAD_LOCK : in bit; SCAN_EN : in bit; PCI_REQ_L : in bit; RX : in bit; TCK : in bit; TMS : in bit; TDI : in bit; TRST_L : in bit; TDO : out bit; VDDI : linkage bit_vector(7 DOWNTO 0); VDDX : linkage bit_vector(7 DOWNTO 0); VDDX_P : linkage bit_vector(3 DOWNTO 0); VDD : linkage bit_vector(11 DOWNTO 0); VSSI : linkage bit_vector(7 DOWNTO 0); VSSX : linkage bit_vector(10 DOWNTO 0); VSSX_P : linkage bit_vector(3 DOWNTO 0); VSS : linkage bit_vector(12 DOWNTO 0) ); use STD_1149_1_1994.all; attribute COMPONENT_CONFORMANCE of DS21285 : entity is "STD_1149_1_1990"; attribute PIN_MAP of DS21285 : entity is PHYSICAL_PIN_MAP; constant BGA_231_PACKAGE : PIN_MAP_STRING := "BA:(B1,D2)," & "MA:(D3,E4,C1,E3,E2,E1,F3,F2,F1,G3,G1,H3,H2)," & "IRQ_IN_L:(J4,J3,J2,J1)," & "CS_L:(L1,L2,L3,L4)," & "D_WREN_L:M1," & "CMD:(M2,M3,M4)," & "ROM_CE_L:N1," & "SCAN_EN:N2," & "XIOW_L:R2," & "XIOR_L:T1," & "XD_WREN_L:P4," & "XCS_L:(R3,T2,U1)," & "RX:U2," & "TX:T3," & "PCI_GNT_L:V1," & "PCI_REQ_L:T4," & "PCI_RST_L:U3," & "PCI_CLK:V2," & "GNT_L:W1," & "REQ_L:V3," & "AD:(W3,Y2,W4,V4,U5,Y3,V5,W5,W6,Y6,V7,Y7,V8,W8,Y8,V9,W13,V13,Y14, " & " W14,V14,W15,Y16,V15,V16,W17,Y18,U16,V17,Y19,V18,W20)," & "CBE_L:(Y5,W9,Y13,Y17)," & "IDSEL:U7," & "FRAME_L:Y9," & "IRDY_L:W10," & "TRDY_L:V10," & "DEVSEL_L:Y10," & "STOP_L:U11," & "PCI_CFN:Y12," & "PERR_L:W12," & "SERR_L:V12," & "PAR:U12," & "PCI_IRQ_L:W16," & "VIO:V19," & "PAD_NIRQ:U19," & "PAD_NFIQ:U18," & "PAD_NRESET:T17," & "PAD_A:(V20,T18,T19,T20,R18,P17,R19,R20,P18,P19,P20,N18,N20,M17,M18,M19," & " M20,L19,L18,L20,K17,J20,J19,J18,J17,H20,H19,H18,G20,G19,F20,F19)," & "PAD_MAS:(E20,G17)," & "PAD_ABE:F18," & "PAD_NRW:E19," & "PAD_LOCK:D20," & "PAD_CLF:E18," & "PAD_OSC:D19," & "PAD_FCLK_IN:C20," & "PAD_NMREQ:A18," & "PAD_DQM:(A17,B13,B9,A5)," & "PAD_PARITY:(C16,A13,D9,C6)," & "PAD_D:(B16,A16,C15,D14,B15,A15,C14,A14,D12,C12,A12,A11,A10,B10,D10,A9," & " A8,B8,C8,A7,B7,A6,C7,B6,B5,A4,C5,B4,A3,D5,B3,C3)," & "PAD_DBE:B14," & "TMS:P2," & "TCK:P3," & "TDI:N3," & "TDO:P1," & "TRST_L:R1," & "NC:H1," & "PAD_FCLK_OUT : D18," & "PAD_MCLK : C19," & "PAD_SDCLK : (C18,A19,B17,C17)," & "VDDI : (A2,A20,C11,K18,K3,V11,Y1,Y20)," & "VDDX : (B12, B18,C10,C2,E17,G4,K20,U20)," & "VDDX_P : (U9,V6,Y11,Y4)," & "VDD : (D06,D11,D15,F04,F17,K04,L17,R04,R17,U06,U10,U15)," & "VSSI : (B11,B19,B2,K19,K2,W11,W19,W2)," & "VSSX : (B20,C13,C4,C9,D1, D16,D7,G18,G2,K1,N19)," & "VSSX_P : (U14,W18,W7,Y15)," & "VSS : (A01,D04,D08,D13,D17,H04,H17,N04,N17,U04,U08,U13,U17)" ; constant numeric_231_PACKAGE : PIN_MAP_STRING := "BA:(21,62), " & "MA:(63,84,41,83,82,81,91,90,89,99,97,107,106), " & "IRQ_IN_L:(116,115,114,113), " & "CS_L:(129,130,131,132), " & "D_WREN_L: 137, " & "CMD:(138, 139, 140), " & "ROM_CE_L: 145, " & "SCAN_EN: 146, " & "XIOW_L: 162, " & "XIOR_L: 169, " & "XD_WREN_L: 156, " & "XCS_L:(163, 170, 177), " & "RX: 178, " & "TX: 171, " & "PCI_GNT_L: 197, " & "PCI_REQ_L: 172, " & "PCI_RST_L: 179, " & "PCI_CLK: 198, " & "GNT_L: 217, " & "REQ_L: 199, " & "AD:(219,238,220,200,181,239,201,221,222,242,203,243,204,224,244,205,229,209,250, " & " 230,210,231,252,211,212,233,254,192,213,255,214,236), " & "CBE_L:(241,225,249,253), " & "IDSEL: 183, " & "FRAME_L: 245, " & "IRDY_L: 226, " & "TRDY_L: 206, " & "DEVSEL_L: 246, " & "STOP_L: 187, " & "PCI_CFN: 248, " & "PERR_L: 228, " & "SERR_L: 208, " & "PAR: 188, " & "PCI_IRQ_L: 232, " & "VIO: 215, " & "PAD_NIRQ: 195, " & "PAD_NFIQ: 194, " & "PAD_NRESET: 173, " & "PAD_A:(216,174,175,176,166,157,167,168,158,159,160,150,152,141,142,143, " & " 144,135,134,136,125,120,119,118,117,112,111,110,104,103,96,95), " & "PAD_MAS:(88,101), " & "PAD_ABE: 94, " & "PAD_NRW: 87, " & "PAD_LOCK: 80, " & "PAD_CLF: 86, " & "PAD_OSC: 79, " & "PAD_FCLK_IN: 60, " & "PAD_NMREQ: 18, " & "PAD_DQM:(17,33,29,5), " & "PAD_PARITY:(56,13,69,46), " & "PAD_D:(36,16,55,74,35,15,54,14,72,52,12,11,10,30,70,9, " & " 8,28,48,7,27,6,47,26,25,4,45,24,3,65,23,43), " & "PAD_DBE: 34, " & "TMS: 154, " & "TCK: 155, " & "TDI: 147, " & "TDO: 153, " & "TRST_L: 161, " & "NC: 105, " & "PAD_FCLK_OUT: 78, " & "PAD_MCLK: 59, " & "PAD_SDCLK: (58,19,37,57), " & "VDDI: (2,20,51,126,123,207,237,256), " & "VDDX: (32,38,50,42,85,100,128,196), " & "VDDX_P: (185,202,247,240), " & "VDD: (66,71,75,92,93,124,133,164,165,182,186,191), " & "VSSI: (31,39,22,127,122,227,235,218), " & "VSSX: (40,53,44,49,61,76,67,102,98,121,151), " & "VSSX_P: (190,234,223,251)," & "VSS: (1,64,68,73,77,108,109,148,149,180,184,189,193)" ; attribute TAP_SCAN_IN of TDI : signal is true; attribute TAP_SCAN_MODE of TMS : signal is true; attribute TAP_SCAN_OUT of TDO : signal is true; attribute TAP_SCAN_CLOCK of TCK : signal is (20.0e6,BOTH); attribute TAP_SCAN_RESET of TRST_L : signal is true; attribute INSTRUCTION_LENGTH of DS21285 : entity is 4; attribute INSTRUCTION_OPCODE of DS21285 : entity is "idcode (0100)," & "clamp (0011)," & "highz (0010)," & "extest (0000)," & "sample (0001)," & "bypass (1111)"; attribute INSTRUCTION_CAPTURE of DS21285 : entity is "0001"; attribute IDCODE_REGISTER of DS21285 : entity is "00010100000110010100000001101011"; attribute BOUNDARY_CELLS of DS21285 : entity is "BC_1, BC_2, BC_4"; attribute BOUNDARY_LENGTH of DS21285 : entity is 360; attribute BOUNDARY_REGISTER of DS21285 : entity is ---------------------------------------------------------------- ---cell cell cntl disable -- num type port function safe cell value rslt ---------------------------------------------------------------- " 0 (BC_4, BA(1), input, X), "& " 1 (BC_1, BA(1), output3, X, 30, 1, Z), "& " 2 (BC_4, BA(0), input, X), "& " 3 (BC_1, BA(0), output3, X, 30, 1, Z), "& " 4 (BC_4, MA(12), input, X), "& " 5 (BC_1, MA(12), output3, X, 30, 1, Z), "& " 6 (BC_4, MA(11), input, X), "& " 7 (BC_1, MA(11), output3, X, 30, 1, Z), "& " 8 (BC_4, MA(10), input, X), "& " 9 (BC_1, MA(10), output3, X, 30, 1, Z), "& " 10 (BC_4, MA(9), input, X), "& " 11 (BC_1, MA(9), output3, X, 30, 1, Z), "& " 12 (BC_4, MA(8), input, X), "& " 13 (BC_1, MA(8), output3, X, 30, 1, Z), "& " 14 (BC_4, MA(7), input, X), "& " 15 (BC_1, MA(7), output3, X, 30, 1, Z), "& " 16 (BC_4, MA(6), input, X), "& " 17 (BC_1, MA(6), output3, X, 30, 1, Z), "& " 18 (BC_4, MA(5), input, X), "& " 19 (BC_1, MA(5), output3, X, 30, 1, Z), "& " 20 (BC_4, MA(4), input, X), "& " 21 (BC_1, MA(4), output3, X, 30, 1, Z), "& " 22 (BC_4, MA(3), input, X), "& " 23 (BC_1, MA(3), output3, X, 30, 1, Z), "& " 24 (BC_4, MA(2), input, X), "& " 25 (BC_1, MA(2), output3, X, 30, 1, Z), "& " 26 (BC_4, MA(1), input, X), "& " 27 (BC_1, MA(1), output3, X, 30, 1, Z), "& " 28 (BC_4, MA(0), input, X), "& " 29 (BC_1, MA(0), output3, X, 30, 1, Z), "& " 30 (BC_2, *, control, X), "& " 31 (BC_4, IRQ_IN_L(3), input, X), "& " 32 (BC_4, IRQ_IN_L(2), input, X), "& " 33 (BC_4, IRQ_IN_L(1), input, X), "& " 34 (BC_4, IRQ_IN_L(0), input, X), "& " 35 (BC_4, *, internal, X), "& " 36 (BC_1, CS_L(3), output3, X, 52, 1, Z), "& " 37 (BC_4, *, internal, X), "& " 38 (BC_1, CS_L(2), output3, X, 52, 1, Z), "& " 39 (BC_4, *, internal, X), "& " 40 (BC_1, CS_L(1), output3, X, 52, 1, Z), "& " 41 (BC_4, *, internal, X), "& " 42 (BC_1, CS_L(0), output3, X, 52, 1, Z), "& " 43 (BC_4, *, internal, X), "& " 44 (BC_1, D_WREN_L, output3, X, 52, 1, Z), "& " 45 (BC_4, *, internal, X), "& " 46 (BC_1, CMD(2), output3, X, 52, 1, Z), "& " 47 (BC_4, *, internal, X), "& " 48 (BC_1, CMD(1), output3, X, 52, 1, Z), "& " 49 (BC_4, *, internal, X), "& " 50 (BC_1, CMD(0), output3, X, 52, 1, Z), "& " 51 (BC_2, *, control, X), "& " 52 (BC_2, *, control, X), "& " 53 (BC_4, *, internal, X), "& " 54 (BC_1, ROM_CE_L, output3, X, 52, 1, Z), "& " 55 (BC_4, SCAN_EN, input, X), "& " 56 (BC_4, XIOW_L, input, X), "& " 57 (BC_1, XIOW_L, output3, X, 51, 1, Z), "& " 58 (BC_4, XIOR_L, input, X), "& " 59 (BC_1, XIOR_L, output3, X, 51, 1, Z), "& " 60 (BC_4, XD_WREN_L, input, X), "& " 61 (BC_1, XD_WREN_L, output3, X, 51, 1, Z), "& " 62 (BC_4, XCS_L(2), input, X), "& " 63 (BC_1, XCS_L(2), output3, X, 70, 1, Z), "& " 64 (BC_4, XCS_L(1), input, X), "& " 65 (BC_1, XCS_L(1), output3, X, 69, 1, Z), "& " 66 (BC_4, XCS_L(0), input, X), "& " 67 (BC_1, XCS_L(0), output3, X, 68, 1, Z), "& " 68 (BC_2, *, control, X), "& " 69 (BC_2, *, control, X), "& " 70 (BC_2, *, control, X), "& " 71 (BC_4, RX, input, X), "& " 72 (BC_4, *, internal, X), "& " 73 (BC_1, TX, output2, X), "& " 74 (BC_4, *, internal, X), "& " 75 (BC_1, PCI_GNT_L, output3, X, 76, 1, Z), "& " 76 (BC_2, *, control, X), "& " 77 (BC_4, PCI_REQ_L, input, X), "& " 78 (BC_4, PCI_RST_L, input, X), "& " 79 (BC_1, PCI_RST_L, output3, X, 80, 1, Z), "& " 80 (BC_2, *, control, X), "& -- following signal captures inverted data, changed to INTERNAL cell -- " 81 (BC_4, PCI_CLK, input, X), "& " 81 (BC_4, *, INTERNAL, X), "& " 82 (BC_4, GNT_L, input, X), "& " 83 (BC_4, REQ_L, input, X), "& " 84 (BC_1, REQ_L, output3, X, 85, 1, Z), "& " 85 (BC_2, *, control, X), "& " 86 (BC_4, AD(31), input, X), "& " 87 (BC_1, AD(31), output3, X, 121, 1, Z), "& " 88 (BC_4, AD(30), input, X), "& " 89 (BC_1, AD(30), output3, X, 121, 1, Z), "& " 90 (BC_4, AD(29), input, X), "& " 91 (BC_1, AD(29), output3, X, 121, 1, Z), "& " 92 (BC_4, AD(28), input, X), "& " 93 (BC_1, AD(28), output3, X, 121, 1, Z), "& " 94 (BC_4, AD(27), input, X), "& " 95 (BC_1, AD(27), output3, X, 121, 1, Z), "& " 96 (BC_4, AD(26), input, X), "& " 97 (BC_1, AD(26), output3, X, 121, 1, Z), "& " 98 (BC_4, AD(25), input, X), "& " 99 (BC_1, AD(25), output3, X, 121, 1, Z), "& " 100 (BC_4, AD(24), input, X), "& " 101 (BC_1, AD(24), output3, X, 121, 1, Z), "& " 102 (BC_4, CBE_L(3), input, X), "& " 103 (BC_1, CBE_L(3), output3, X, 171, 1, Z), "& " 104 (BC_4, IDSEL, input, X), "& " 105 (BC_4, AD(23), input, X), "& " 106 (BC_1, AD(23), output3, X, 121, 1, Z), "& " 107 (BC_4, AD(22), input, X), "& " 108 (BC_1, AD(22), output3, X, 121, 1, Z), "& " 109 (BC_4, AD(21), input, X), "& " 110 (BC_1, AD(21), output3, X, 121, 1, Z), "& " 111 (BC_4, AD(20), input, X), "& " 112 (BC_1, AD(20), output3, X, 121, 1, Z), "& " 113 (BC_4, AD(19), input, X), "& " 114 (BC_1, AD(19), output3, X, 121, 1, Z), "& " 115 (BC_4, AD(18), input, X), "& " 116 (BC_1, AD(18), output3, X, 121, 1, Z), "& " 117 (BC_4, AD(17), input, X), "& " 118 (BC_1, AD(17), output3, X, 121, 1, Z), "& " 119 (BC_4, AD(16), input, X), "& " 120 (BC_1, AD(16), output3, X, 121, 1, Z), "& " 121 (BC_2, *, control, X), "& " 122 (BC_4, CBE_L(2), input, X), "& " 123 (BC_1, CBE_L(2), output3, X, 171, 1, Z), "& " 124 (BC_4, FRAME_L, input, X), "& " 125 (BC_1, FRAME_L, output3, X, 126, 1, Z), "& " 126 (BC_2, *, control, X), "& " 127 (BC_4, IRDY_L, input, X), "& " 128 (BC_1, IRDY_L, output3, X, 129, 1, Z), "& " 129 (BC_2, *, control, X), "& " 130 (BC_4, TRDY_L, input, X), "& " 131 (BC_1, TRDY_L, output3, X, 132, 1, Z), "& " 132 (BC_2, *, control, X), "& " 133 (BC_4, DEVSEL_L, input, X), "& " 134 (BC_1, DEVSEL_L, output3, X, 132, 1, Z), "& " 135 (BC_4, STOP_L, input, X), "& " 136 (BC_1, STOP_L, output3, X, 132, 1, Z), "& " 137 (BC_4, PCI_CFN, input, X), "& " 138 (BC_4, PERR_L, input, X), "& " 139 (BC_1, PERR_L, output3, X, 140, 1, Z), "& " 140 (BC_2, *, control, X), "& " 141 (BC_4, SERR_L, input, X), "& " 142 (BC_1, SERR_L, output3, X, 143, 1, Z), "& " 143 (BC_2, *, control, X), "& " 144 (BC_4, PAR, input, X), "& " 145 (BC_1, PAR, output3, X, 146, 1, Z), "& " 146 (BC_2, *, control, X), "& " 147 (BC_4, CBE_L(1), input, X), "& " 148 (BC_1, CBE_L(1), output3, X, 171, 1, Z), "& " 149 (BC_4, AD(15), input, X), "& " 150 (BC_1, AD(15), output3, X, 151, 1, Z), "& " 151 (BC_2, *, control, X), "& " 152 (BC_4, AD(14), input, X), "& " 153 (BC_1, AD(14), output3, X, 151, 1, Z), "& " 154 (BC_4, AD(13), input, X), "& " 155 (BC_1, AD(13), output3, X, 151, 1, Z), "& " 156 (BC_4, AD(12), input, X), "& " 157 (BC_1, AD(12), output3, X, 151, 1, Z), "& " 158 (BC_4, AD(11), input, X), "& " 159 (BC_1, AD(11), output3, X, 151, 1, Z), "& " 160 (BC_4, AD(10), input, X), "& " 161 (BC_1, AD(10), output3, X, 151, 1, Z), "& " 162 (BC_4, AD(9), input, X), "& " 163 (BC_1, AD(9), output3, X, 151, 1, Z), "& " 164 (BC_4, AD(8), input, X), "& " 165 (BC_1, AD(8), output3, X, 151, 1, Z), "& " 166 (BC_4, PCI_IRQ_L, input, X), "& " 167 (BC_1, PCI_IRQ_L, output3, X, 168, 1, Z), "& " 168 (BC_2, *, control, X), "& " 169 (BC_4, CBE_L(0), input, X), "& " 170 (BC_1, CBE_L(0), output3, X, 171, 1,Z), "& " 171 (BC_2, *, control, X), "& " 172 (BC_4, AD(7), input, X), "& " 173 (BC_1, AD(7), output3, X, 151, 1, Z), "& " 174 (BC_4, AD(6), input, X), "& " 175 (BC_1, AD(6), output3, X, 151, 1, Z), "& " 176 (BC_4, AD(5), input, X), "& " 177 (BC_1, AD(5), output3, X, 151, 1, Z), "& " 178 (BC_4, AD(4), input, X), "& " 179 (BC_1, AD(4), output3, X, 151, 1, Z), "& " 180 (BC_4, AD(3), input, X), "& " 181 (BC_1, AD(3), output3, X, 151, 1, Z), "& " 182 (BC_4, AD(2), input, X), "& " 183 (BC_1, AD(2), output3, X, 151, 1, Z), "& " 184 (BC_4, AD(1), input, X), "& " 185 (BC_1, AD(1), output3, X, 151, 1, Z), "& " 186 (BC_4, AD(0), input, X), "& " 187 (BC_1, AD(0), output3, X, 151, 1, Z), "& -- following signal captures analog data, changed to INTERNAL cell -- " 188 (BC_4, VIO, input, X), "& " 188 (BC_4, *, INTERNAL, X), "& " 189 (BC_4, *, internal, X), "& " 190 (BC_1, PAD_NIRQ, output3, X, 52, 1, Z), "& " 191 (BC_4, *, internal, X), "& " 192 (BC_1, PAD_NFIQ, output3, X, 52, 1, Z), "& " 193 (BC_4, PAD_NRESET, input, X), "& " 194 (BC_2, *, control, X), "& " 195 (BC_1, PAD_NRESET, output3, X, 194, 1, Z), "& " 196 (BC_4, PAD_A(31), input, X), "& " 197 (BC_1, PAD_A(31), output3, X, 265, 1, Z), "& " 198 (BC_4, PAD_A(30), input, X), "& " 199 (BC_1, PAD_A(30), output3, X, 265, 1, Z), "& " 200 (BC_4, PAD_A(29), input, X), "& " 201 (BC_1, PAD_A(29), output3, X, 265, 1, Z), "& " 202 (BC_4, PAD_A(28), input, X), "& " 203 (BC_1, PAD_A(28), output3, X, 265, 1, Z), "& " 204 (BC_4, PAD_A(27), input, X), "& " 205 (BC_1, PAD_A(27), output3, X, 265, 1, Z), "& " 206 (BC_4, PAD_A(26), input, X), "& " 207 (BC_1, PAD_A(26), output3, X, 265, 1, Z), "& " 208 (BC_4, PAD_A(25), input, X), "& " 209 (BC_1, PAD_A(25), output3, X, 265, 1, Z), "& " 210 (BC_4, PAD_A(24), input, X), "& " 211 (BC_1, PAD_A(24), output3, X, 265, 1, Z), "& " 212 (BC_4, PAD_A(23), input, X), "& " 213 (BC_1, PAD_A(23), output3, X, 265, 1, Z), "& " 214 (BC_4, PAD_A(22), input, X), "& " 215 (BC_1, PAD_A(22), output3, X, 265, 1, Z), "& " 216 (BC_4, PAD_A(21), input, X), "& " 217 (BC_1, PAD_A(21), output3, X, 265, 1, Z), "& " 218 (BC_4, PAD_A(20), input, X), "& " 219 (BC_1, PAD_A(20), output3, X, 265, 1, Z), "& " 220 (BC_4, PAD_A(19), input, X), "& " 221 (BC_1, PAD_A(19), output3, X, 265, 1, Z), "& " 222 (BC_4, PAD_A(18), input, X), "& " 223 (BC_1, PAD_A(18), output3, X, 265, 1, Z), "& " 224 (BC_4, PAD_A(17), input, X), "& " 225 (BC_1, PAD_A(17), output3, X, 265, 1, Z), "& " 226 (BC_4, PAD_A(16), input, X), "& " 227 (BC_1, PAD_A(16), output3, X, 265, 1, Z), "& " 228 (BC_4, PAD_A(15), input, X), "& " 229 (BC_1, PAD_A(15), output3, X, 265, 1, Z), "& " 230 (BC_4, PAD_A(14), input, X), "& " 231 (BC_1, PAD_A(14), output3, X, 264, 1, Z), "& " 232 (BC_4, PAD_A(13), input, X), "& " 233 (BC_1, PAD_A(13), output3, X, 264, 1, Z), "& " 234 (BC_4, PAD_A(12), input, X), "& " 235 (BC_1, PAD_A(12), output3, X, 264, 1, Z), "& " 236 (BC_4, PAD_A(11), input, X), "& " 237 (BC_1, PAD_A(11), output3, X, 264, 1, Z), "& " 238 (BC_4, PAD_A(10), input, X), "& " 239 (BC_1, PAD_A(10), output3, X, 264, 1, Z), "& " 240 (BC_4, PAD_A(9), input, X), "& " 241 (BC_1, PAD_A(9), output3, X, 264, 1, Z), "& " 242 (BC_4, PAD_A(8), input, X), "& " 243 (BC_1, PAD_A(8), output3, X, 264, 1, Z), "& " 244 (BC_4, PAD_A(7), input, X), "& " 245 (BC_1, PAD_A(7), output3, X, 264, 1, Z), "& " 246 (BC_4, PAD_A(6), input, X), "& " 247 (BC_1, PAD_A(6), output3, X, 264, 1, Z), "& " 248 (BC_4, PAD_A(5), input, X), "& " 249 (BC_1, PAD_A(5), output3, X, 264, 1, Z), "& " 250 (BC_4, PAD_A(4), input, X), "& " 251 (BC_1, PAD_A(4), output3, X, 264, 1, Z), "& " 252 (BC_4, PAD_A(3), input, X), "& " 253 (BC_1, PAD_A(3), output3, X, 264, 1, Z), "& " 254 (BC_4, PAD_A(2), input, X), "& " 255 (BC_1, PAD_A(2), output3, X, 264, 1, Z), "& " 256 (BC_4, PAD_A(1), input, X), "& " 257 (BC_1, PAD_A(1), output3, X, 264, 1, Z), "& " 258 (BC_4, PAD_A(0), input, X), "& " 259 (BC_1, PAD_A(0), output3, X, 264, 1, Z), "& " 260 (BC_4, PAD_MAS(1), input, X), "& " 261 (BC_1, PAD_MAS(0), output3, X, 264, 1, Z), "& " 262 (BC_1, PAD_MAS(1), output3, X, 264, 1, Z), "& " 263 (BC_4, PAD_MAS(0), input, X), "& " 264 (BC_2, *, control, X), "& " 265 (BC_2, *, control, X), "& " 266 (BC_4, *, internal, X), "& " 267 (BC_1, PAD_ABE, output3, X, 52, 1, Z), "& " 268 (BC_4, PAD_NRW, input, X), "& " 269 (BC_4, PAD_LOCK, input, X), "& " 270 (BC_4, PAD_CLF, input, X), "& " 271 (BC_1, PAD_OSC, input, X), "& -- following signal captures inverted data, changed to INTERNAL cell -- " 272 (BC_4, PAD_FCLK_IN, input, X), "& " 272 (BC_4, *, INTERNAL, X), "& " 273 (BC_4, PAD_NMREQ, input, X), "& " 274 (BC_4, *, internal, X), "& " 275 (BC_1, PAD_DQM(3), output3, X, 52, 1, Z), "& " 276 (BC_4, PAD_PARITY(3), input, X), "& " 277 (BC_1, PAD_PARITY(3), output3, X, 278, 1, Z), "& " 278 (BC_2, *, control, X), "& " 279 (BC_4, PAD_D(31), input, X), "& " 280 (BC_1, PAD_D(31), output3, X, 317, 1, Z), "& " 281 (BC_4, PAD_D(30), input, X), "& " 282 (BC_1, PAD_D(30), output3, X, 317, 1, Z), "& " 283 (BC_4, PAD_D(29), input, X), "& " 284 (BC_1, PAD_D(29), output3, X, 317, 1, Z), "& " 285 (BC_4, PAD_D(28), input, X), "& " 286 (BC_1, PAD_D(28), output3, X, 317, 1, Z), "& " 287 (BC_4, PAD_D(27), input, X), "& " 288 (BC_1, PAD_D(27), output3, X, 317, 1, Z), "& " 289 (BC_4, PAD_D(26), input, X), "& " 290 (BC_1, PAD_D(26), output3, X, 317, 1, Z), "& " 291 (BC_4, PAD_D(25), input, X), "& " 292 (BC_1, PAD_D(25), output3, X, 317, 1, Z), "& " 293 (BC_4, *, internal, X), "& " 294 (BC_1, PAD_DBE, output3, X, 52, 1, Z), "& " 295 (BC_4, PAD_D(24), input, X), "& " 296 (BC_1, PAD_D(24), output3, X, 317, 1, Z), "& " 297 (BC_4, *, internal, X), "& " 298 (BC_1, PAD_DQM(2), output3, X, 52, 1, Z), "& " 299 (BC_4, PAD_PARITY(2), input, X), "& " 300 (BC_1, PAD_PARITY(2), output3, X, 278, 1, Z), "& " 301 (BC_4, PAD_D(23), input, X), "& " 302 (BC_1, PAD_D(23), output3, X, 317, 1, Z), "& " 303 (BC_4, PAD_D(22), input, X), "& " 304 (BC_1, PAD_D(22), output3, X, 317, 1, Z), "& " 305 (BC_4, PAD_D(21), input, X), "& " 306 (BC_1, PAD_D(21), output3, X, 317, 1, Z), "& " 307 (BC_4, PAD_D(20), input, X), "& " 308 (BC_1, PAD_D(20), output3, X, 317, 1, Z), "& " 309 (BC_4, PAD_D(19), input, X), "& " 310 (BC_1, PAD_D(19), output3, X, 317, 1, Z), "& " 311 (BC_4, PAD_D(18), input, X), "& " 312 (BC_1, PAD_D(18), output3, X, 317, 1, Z), "& " 313 (BC_4, PAD_D(17), input, X), "& " 314 (BC_1, PAD_D(17), output3, X, 317, 1, Z), "& " 315 (BC_4, PAD_D(16), input, X), "& " 316 (BC_1, PAD_D(16), output3, X, 317, 1, Z), "& " 317 (BC_2, *, control, X), "& " 318 (BC_4, *, internal, X), "& " 319 (BC_1, PAD_DQM(1), output3, X, 52, 1, Z), "& " 320 (BC_4, PAD_PARITY(1), input, X), "& " 321 (BC_1, PAD_PARITY(1), output3, X, 278, 1, Z), "& " 322 (BC_4, PAD_D(15), input, X), "& " 323 (BC_1, PAD_D(15), output3, X, 338, 1, Z), "& " 324 (BC_4, PAD_D(14), input, X), "& " 325 (BC_1, PAD_D(14), output3, X, 338, 1, Z), "& " 326 (BC_4, PAD_D(13), input, X), "& " 327 (BC_1, PAD_D(13), output3, X, 338, 1, Z), "& " 328 (BC_4, PAD_D(12), input, X), "& " 329 (BC_1, PAD_D(12), output3, X, 338, 1, Z), "& " 330 (BC_4, PAD_D(11), input, X), "& " 331 (BC_1, PAD_D(11), output3, X, 338, 1, Z), "& " 332 (BC_4, PAD_D(10), input, X), "& " 333 (BC_1, PAD_D(10), output3, X, 338, 1, Z), "& " 334 (BC_4, PAD_D(9), input, X), "& " 335 (BC_1, PAD_D(9), output3, X, 338, 1, Z), "& " 336 (BC_4, PAD_D(8), input, X), "& " 337 (BC_1, PAD_D(8), output3, X, 338, 1, Z), "& " 338 (BC_2, *, control, X), "& " 339 (BC_4, *, internal, X), "& " 340 (BC_1, PAD_DQM(0), output3, X, 52, 1, Z), "& " 341 (BC_4, PAD_PARITY(0), input, X), "& " 342 (BC_1, PAD_PARITY(0), output3, X, 278, 1, Z), "& " 343 (BC_4, PAD_D(7), input, X), "& " 344 (BC_1, PAD_D(7), output3, X, 359, 1, Z), "& " 345 (BC_4, PAD_D(6), input, X), "& " 346 (BC_1, PAD_D(6), output3, X, 359, 1, Z), "& " 347 (BC_4, PAD_D(5), input, X), "& " 348 (BC_1, PAD_D(5), output3, X, 359, 1, Z), "& " 349 (BC_4, PAD_D(4), input, X), "& " 350 (BC_1, PAD_D(4), output3, X, 359, 1, Z), "& " 351 (BC_4, PAD_D(3), input, X), "& " 352 (BC_1, PAD_D(3), output3, X, 359, 1, Z), "& " 353 (BC_4, PAD_D(2), input, X), "& " 354 (BC_1, PAD_D(2), output3, X, 359, 1, Z), "& " 355 (BC_4, PAD_D(1), input, X), "& " 356 (BC_1, PAD_D(1), output3, X, 359, 1, Z), "& " 357 (BC_4, PAD_D(0), input, X), "& " 358 (BC_1, PAD_D(0), output3, X, 359, 1, Z), "& " 359 (BC_2, *, control, X)" ; end DS21285;